One of the most complicated things on VHDL is forwarding a data from one clock domain to another.
There are different ways to handle this issue, i will talk of the most common ones.
First way- the Easy way:
We all know FIFOs for many years. In the VIVADO(Xilinx FPGAs tool) and Quartus(Intel FPGAs tool) you can find different type of FIFOs.
What we need is a FIFOs that can accept 2 different clock domain, one for READ and the other for Write.
In this way we can Write in one clock and Read it with the other.
For VIVADO, the right FIFO for you will be "FIFO Generator".
The FIFO way has it's own problems, such as moving data from fast clock domain to a slow clock domain, it might cause the FIFO full if the data is streaming all the time.
Second way- the Hard way:
Writing the data with one clock and sampling it with the second clock with a simple process.
The only thing you need to be aware of is that you might sample the data when it has just changed. This behavior means that you will need to sample the data twice for it to be reliable and stable. you can see here how it looks like with 2 flipflops sampling the data: https://en.wikipedia.org/wiki/Metastability_(electronics)#/media/File:Metastability_D-Flipflops.svg
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